Predefined macros in Makefiles.

MAKE - current make program name

$?   - list of dependencies, can be used in target rules
$@   - current target name, can be used in target rules
$<   - target prerequisite, can be used in target rules
$*   - name without suffix, can be used in target rules
$%   - name corresponding .o file, can be used in target rules
@D   - directory part of target name, can be used in target rules
@F   - file name part of target name, can be used in target rules
$$va - make strips first $ and sends $va to shell, contents of var.